Power consumption reduction in a SDR based wireless communication system using partial reconfigurable FPGA

The increase in the consumer demand and the exponential growth for wireless systems, which enables consumer to communicate in any place by means of information, has in turn led to the emergence of many portable wireless communication products. The present research works primarily targets to integrate as much as signal processing applications in a single portable device. Since integration through software applications compromises system speed, integration through hardware will be the better compliment. Software Defined Radio (SDR) Technology yields to achieve this small form factor system while keeping power consumption under the limit. SDR enables soft changeable system functionality, such as receiver demodulation technique .In this implementation two type modulation techniques are used, ASK and FSK. The flexibility of changing the receiver functionality in runtime is usually attained by FPGA. However, using a complete FPGA for reconfiguration of a particular functionality is not an efficient method in terms of power consumption and switching time. We proposed a SDR architecture using a recent advancement in FPGAs, called Partial Reconfiguration (PR). PR helps to change certain portion of FPGA, while the rest keeps functioning. It also reduces the total hardware usage and hence the power. The different demodulation technique and other signal processing application from an external memory unit can be loaded into FPGA PR modules while the other parts of FPGA doing a constant data processing.